Embodiments of the inventive concept relate to data processing methods for nonvolatile memory systems. More particularly, embodiments of the inventive concept relate to data processing methods for nonvolatile memory systems that are capable of maximizing the performance of constituent firmware by simultaneously updating metadata after a file data transfer between a host Central Processing Unit (CPU) and a memory.
Semiconductor memory devices may be classified as volatile memories such as DRAM, SRAM, etc., and nonvolatile such as EEPROM, FRAM, PRAM, flash memory, etc. Volatile memory loses stored data in the absence of applied power, while nonvolatile memory is able to retain stored data even in the absence of applied power. One or more memory device(s) are typically accessed in a memory system by a controller or interface.
Recent consumer trends are towards devices, and mobile devices in particular, that incorporate nonvolatile memory systems and devices. For example, nonvolatile memory systems and devices are commonly used in MP3 players, digital cameras, mobile phones, camcorders, flash cards, solid state disks, etc.
In particular, so-called flash memory, being one type of nonvolatile memory, has been widely adapted for use as a storage medium in digital data systems due to its combination of high programming speed, low power consumption, a mass storage capacity, etc.
FIG. 1 is a block diagram illustrating a flash memory system as one example of a conventional nonvolatile memory system.
Referring to FIG. 1, a nonvolatile memory system 100 comprises a flash memory device 140 and an application specific integrated circuit (ASIC) 130 serving as an interface to the flash memory device 140. In the example of FIG. 1, the nonvolatile memory system 100 is shown connected via a host interface with a host CPU 110 and a DRAM 120. The host CPU 110 typically provides commands (e.g., read, write and erase commands, etc.) to the flash memory 140 via the ASIC 130 and the host interface. In this context, a “command” may be variously communicated as one or more control signals and/or one or more data packets.
The ASIC 130 may be a memory controller. For example, when receiving a write command from the host CPU 110, the ASIC 130 may be used to control the flash memory 140 such that file data received from the host CPU 110 is written to the flash memory 140 via a flash interface.
FIG. 2A is a block diagram further describing one possible relationship between a file system 115 run on the host CPU 110 and a flash translation layer (FTL) 135 run by the ASIC 130. As is conventionally understood, the file system 115 is generally capable of managing files and associated file data resulting from the execution of one or more applications on the host CPU. As is also conventionally understood, the FTL 135 is used to manage memory space in the flash memory 140 by, among other functions, translating (or “mapping”) logical addresses used by the file system 115 and/or host CPU 110 into physical addresses used to store data in the flash memory 140.
Thus, in response to various commands issued by the host CPU 110, the file system 115 manages the use of the flash memory 140 through the functionality provided by the host interface, the FTL 135 and the flash interface, wherein the ASIC 130 is integral to the operation of the host interface and flash interface.
FIG. 2B is a conceptual diagram describing one possible organization of file data during a program (or write) operation performed by the flash memory system 100. Referring to FIGS. 1, 2A and 2B, file data (e.g., data segments DO through D7) during a program operation may include certain metadata updates. That is, “input data” (or payload data) of the sort communicated to the flash memory 140 during a program operation may include a plurality of data segments (D0 through D7) and one or more related metadata update instructions. The term “segment” is used here to generically identify input data of any reasonable size and/or particular composition.
According to the example of FIG. 2B, the file system 115 generates logical addresses for each input data segments D0 to D7 in response to a write request provided by the host CPU 110. Upon receiving the input data segments, the FTL maps the corresponding logical addresses generated by the file system 115 onto physical addresses for the flash memory 140.
Thus, the FTL 135 may program the first data segment D0 in the flash memory 140 and update certain metadata related to the first data segment. This approach is used for each one of the plurality of input data segments D0 through D7. Accordingly, the eight (8) input data segments (D0 through D7) provided by the file system 115 in the example of FIG. 2B result in eight (8) corresponding metadata update instructions being sent to the flash memory 140 and eight (8) corresponding execution periods, one for each metadata update.
However, as nonvolatile memory systems are increasingly used to store large volumes of user data, particularly in mobile devices such as cellular phones, the effective number of input data segments being programmed to memory has dramatically increased. The resulting large number of metadata updates slows memory system performance and firmware operation in particular.